1 files changed, 31 insertions, 4 deletions

diff --git a/coreboot-x201.mdwn b/coreboot-x201.mdwn
index bebc685..6a8809a 100644
--- a/coreboot-x201.mdwn
+++ b/coreboot-x201.mdwn
@@ -56,9 +56,36 @@ dd if=flash.bin of=coreboot/3rdparty/mainboard/lenovo/x201/me.bin \
 - extract vgabios.bin from BIOS (I used PhoenixTool for this, as the included bios extractor from coreboot didn't work for me) 
 - hint: [[SWIM|http://www.urbandictionary.com/define.php?term=swim]] uploaded it [[somewhere|https://www.google.de/search?q=63b3bcf7296acc1be44a1b7b1b5e7897]] in the internets
 - use your prior version number for local version string (e.g [["6QET70WW (1.40)"|http://www.thinkwiki.org/wiki/List_of_DMI_IDs]])
-- at least UNCHECK fake IFD and specify paths to descriptor / ME, select SeaBIOS as payload, use vgabios.bin
-
-- [[compile coreboot|http://www.coreboot.org/Build_HOWTO]]
+- at least UNCHECK fake IFD and specify paths to descriptor / ME
+- select SeaBIOS as payload
+- DO NOT FORGET vgabios.bin
+- USB boot won't work with the SeaBIOS version included in coreboot, so use this fix:
+[[!format diff """
+diff --git a/src/southbridge/intel/bd82x6x/usb_ehci.c b/src/southbridge/intel/bd82x6x/usb_ehci.c
+index 78f92d9..4162562 100644
+--- a/src/southbridge/intel/bd82x6x/usb_ehci.c
++++ b/src/southbridge/intel/bd82x6x/usb_ehci.c
+@@ -38,6 +38,7 @@ static void usb_ehci_init(struct device *dev)
+        printk(BIOS_DEBUG, "EHCI: Setting up controller.. ");
+        reg32 = pci_read_config32(dev, PCI_COMMAND);
+        reg32 |= PCI_COMMAND_MASTER;
++       reg32 |= PCI_COMMAND_MEMORY;
+        //reg32 |= PCI_COMMAND_SERR;
+        pci_write_config32(dev, PCI_COMMAND, reg32);
+ 
+diff --git a/src/southbridge/intel/ibexpeak/usb_ehci.c b/src/southbridge/intel/ibexpeak/usb_ehci.c
+index 7dc7b03..4d1183d 100644
+--- a/src/southbridge/intel/ibexpeak/usb_ehci.c
++++ b/src/southbridge/intel/ibexpeak/usb_ehci.c
+@@ -47,6 +47,7 @@ static void usb_ehci_init(struct device *dev)
+ 
+        reg32 = pci_read_config32(dev, PCI_COMMAND);
+        reg32 |= PCI_COMMAND_MASTER;
++       reg32 |= PCI_COMMAND_MEMORY;
+        //reg32 |= PCI_COMMAND_SERR;
+        pci_write_config32(dev, PCI_COMMAND, reg32);
+"""]]
+- [[compile coreboot|http://www.coreboot.org/Build_HOWTO]] (you'll need gcc-multilib and your /usr/bin/python should point to python2, else use venv)
 - flash resulting ROM image 
 [[!format bash """ 
-flashrom -r bios.bin -pinternal:laptop=force_I_want_a_brick """]]
+flashrom -w coreboot/build/coreboot.rom -pinternal:laptop=force_I_want_a_brick """]]