From b36bc0432d830837e55cbf44077dd660b2a8567b Mon Sep 17 00:00:00 2001 From: jackrandom Date: Tue, 8 Apr 2014 12:52:15 +0200 Subject: USB Boot patch now obsolete --- coreboot-x201.mdwn | 30 ++---------------------------- 1 file changed, 2 insertions(+), 28 deletions(-) diff --git a/coreboot-x201.mdwn b/coreboot-x201.mdwn index 0d588ea..24dd422 100644 --- a/coreboot-x201.mdwn +++ b/coreboot-x201.mdwn @@ -57,41 +57,15 @@ dd if=flash.bin of=coreboot/3rdparty/mainboard/lenovo/x201/me.bin \ skip=12288 count=5230592 bs=1M iflag=count_bytes,skip_bytes """]] - extract vgabios.bin from BIOS (I used [[PhoenixTool|http://forums.mydigitallife.info/threads/13194-Tool-to-Insert-Replace-SLIC-in-Phoenix-Insyde-Dell-EFI-BIOSes]] in a WinBitch VM for this, as the included bios extractor from coreboot didn't work for me) -- hint [[SWIM|http://www.urbandictionary.com/define.php?term=swim]] [[uploaded|http://www.datafilehost.com/d/4c01e3d8]] [[it|http://bitshare.com/?f=i4xwzphy]] [[somewhere|http://www2.zippyshare.com/v/88473898/file.html]] in the internets +- hint [[SWIM|http://www.urbandictionary.com/define.php?term=swim]] [[uploaded|http://www.datafilehost.com/d/4c01e3d8]] [[it|http://sendfile.su/949824]] [[somewhere|http://fbx.ro/sseikovp02nh3ds2]] in the internets - use your prior version number for local version string (e.g [["6QET70WW (1.40)"|http://www.thinkwiki.org/wiki/List_of_DMI_IDs]]) - at least UNCHECK fake IFD and specify paths to descriptor / ME - select SeaBIOS as payload - DO NOT FORGET vgabios.bin -- USB boot won't work with the SeaBIOS version included in coreboot, so use this fix (or choose SeaBIOS master version): -[[!format diff """ -diff --git a/src/southbridge/intel/bd82x6x/usb_ehci.c b/src/southbridge/intel/bd82x6x/usb_ehci.c -index 78f92d9..4162562 100644 ---- a/src/southbridge/intel/bd82x6x/usb_ehci.c -+++ b/src/southbridge/intel/bd82x6x/usb_ehci.c -@@ -38,6 +38,7 @@ static void usb_ehci_init(struct device *dev) - printk(BIOS_DEBUG, "EHCI: Setting up controller.. "); - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER; -+ reg32 |= PCI_COMMAND_MEMORY; - //reg32 |= PCI_COMMAND_SERR; - pci_write_config32(dev, PCI_COMMAND, reg32); - -diff --git a/src/southbridge/intel/ibexpeak/usb_ehci.c b/src/southbridge/intel/ibexpeak/usb_ehci.c -index 7dc7b03..4d1183d 100644 ---- a/src/southbridge/intel/ibexpeak/usb_ehci.c -+++ b/src/southbridge/intel/ibexpeak/usb_ehci.c -@@ -47,6 +47,7 @@ static void usb_ehci_init(struct device *dev) - - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER; -+ reg32 |= PCI_COMMAND_MEMORY; - //reg32 |= PCI_COMMAND_SERR; - pci_write_config32(dev, PCI_COMMAND, reg32); -"""]] - [[compile coreboot|http://www.coreboot.org/Build_HOWTO]] (you'll need gcc-multilib and your python bin should point to python2, else create a venv) - flash resulting ROM image with [[!format bash """ -flashrom -w coreboot/build/coreboot.rom -pinternal:laptop=force_I_want_a_brick """]] +flashrom -c $Chip -w coreboot/build/coreboot.rom -p internal:laptop=force_I_want_a_brick """]] ## additional pics -- cgit v1.2.1