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## n00bie guide for getting coreboot to an x201{i/s/t}
###why would I want this?
- free open source BIOS / EFI implementation
- fast (faster than lenovo BIOS)
- no whitelist restrictions (wifi cards etc.)
- you can boot even with HD-password (for example to change/delete it)
- hotswap harddrive (didn't test, but should work)
- it's cool.
###okay, show me how!
#### preliminary
first you should update your existing BIOS. This is important as you cannot update your ECP version afterwards. Linux users can use the iso files provided by lenovo and do some nice trick described [[here|http://www.thinkwiki.org/wiki/BIOS_update_without_optical_disk]]
It is also advisable to save the output of dmidecode somewhere, as you need specific BIOS versions strings to get thinkpad_acpi to work.
next buy or build a SPI flasher and get a SOIC8 clip for mounting the chip correctly.
#### the ugly part
we have to dump the existing BIOS using [[flashrom|http://www.flashrom.org]] and an external SPI flasher.
here's the pinout:
[[!format bash """
=== front (display) ====
3.3V N/C CLK MOSI
| | | |
| | | |
CS MISO N/C ground
=== back (touchpad) ===
"""]]
[[!img bus_pirate.jpg align="right" size="" alt="buspirate attached"]]
Now it should look similar to this:
You probably have to adjust your contacts quite often for it to work, so don't give up ;)
now read your chip at least twice
[[!format bash """
flashrom -p <yourprogrammer> -r flash.bin
flashrom -p <yourprogrammer> -r flash2.bin
diff flash.bin flash2.bin
"""]]
If the files differ, check your cables.
#### easy part
- extract descriptor / intel ME
[[!format bash """
dd if=flash.bin of=coreboot/3rdparty/mainboard/lenovo/x201/descriptor.bin \
count=12288 bs=1M iflag=count_bytes
dd if=flash.bin of=coreboot/3rdparty/mainboard/lenovo/x201/me.bin \
skip=12288 count=5230592 bs=1M iflag=count_bytes,skip_bytes
"""]]
- extract vgabios.bin from BIOS (I used PhoenixTool for this, as the included bios extractor from coreboot didn't work for me)
- hint: [[SWIM|http://www.urbandictionary.com/define.php?term=swim]] uploaded it [[somewhere|https://www.google.de/search?q=63b3bcf7296acc1be44a1b7b1b5e7897]] in the internets
- use your prior version number for local version string (e.g [["6QET70WW (1.40)"|http://www.thinkwiki.org/wiki/List_of_DMI_IDs]])
- at least UNCHECK fake IFD and specify paths to descriptor / ME
- select SeaBIOS as payload
- DO NOT FORGET vgabios.bin
- USB boot won't work with the SeaBIOS version included in coreboot, so use this fix:
[[!format diff """
diff --git a/src/southbridge/intel/bd82x6x/usb_ehci.c b/src/southbridge/intel/bd82x6x/usb_ehci.c
index 78f92d9..4162562 100644
--- a/src/southbridge/intel/bd82x6x/usb_ehci.c
+++ b/src/southbridge/intel/bd82x6x/usb_ehci.c
@@ -38,6 +38,7 @@ static void usb_ehci_init(struct device *dev)
printk(BIOS_DEBUG, "EHCI: Setting up controller.. ");
reg32 = pci_read_config32(dev, PCI_COMMAND);
reg32 |= PCI_COMMAND_MASTER;
+ reg32 |= PCI_COMMAND_MEMORY;
//reg32 |= PCI_COMMAND_SERR;
pci_write_config32(dev, PCI_COMMAND, reg32);
diff --git a/src/southbridge/intel/ibexpeak/usb_ehci.c b/src/southbridge/intel/ibexpeak/usb_ehci.c
index 7dc7b03..4d1183d 100644
--- a/src/southbridge/intel/ibexpeak/usb_ehci.c
+++ b/src/southbridge/intel/ibexpeak/usb_ehci.c
@@ -47,6 +47,7 @@ static void usb_ehci_init(struct device *dev)
reg32 = pci_read_config32(dev, PCI_COMMAND);
reg32 |= PCI_COMMAND_MASTER;
+ reg32 |= PCI_COMMAND_MEMORY;
//reg32 |= PCI_COMMAND_SERR;
pci_write_config32(dev, PCI_COMMAND, reg32);
"""]]
- [[compile coreboot|http://www.coreboot.org/Build_HOWTO]] (you'll need gcc-multilib and your /usr/bin/python should point to python2, else use venv)
- flash resulting ROM image
[[!format bash """
flashrom -w coreboot/build/coreboot.rom -pinternal:laptop=force_I_want_a_brick """]]
## pics
[[!img chip_location.jpg alt="Chip location"]]
[[!img soic_clip.jpg alt="SOIC mount"]]
[[!img self_build_spi.jpg alt="SPI flasher"]]
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